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W9864G6JH
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
COMMAND
GENERATOR
CAS
DECODER
WE
A10
COLUMN DECODER
CELL ARRAY
BANK #0
COLUMN DECODER
CELL ARRAY
BANK #1
A0
A9
A11
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
BS0
BS1
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ15
REFRESH
COUNTER
COLUMN
COUNTER
NOTE:
UDQM
LDQM
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
CELL ARRAY
BANK #2
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
The cell array configuration is 4096 * 256 * 16
Publication Release Date: Jun. 25, 2013
-6-
Revision A04
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